Synthetiseren van de pipelined mMIPS processor

Synthetiseren van de pipelined mMIPS processor
Sander Stuijk
Department of Electrical Engineering
Electronic Systems
mMIPS
if_pc
2
id_pc
1
add2
shiftleft
imm2word
id_immediate
dev_*
id_instr_25_0
rom_addr
1
2
mux5
0
shiftleft_
jmp
0
mux1
pc
add1
c4
ram_dout
ram_wait
[25-21]
ram_din
id_data_reg1
1
w
r_data_reg2
0
id_data_reg2
b
alu
[15-0]
[25-0]
ram_r
ram_w
mem_dmem_data
hi
lo
2
2
decoder
0
1
[5-0]
1
id_instr_15_11
hazard_ctrl
ctrl
Enable
rst
mem_regdst_addr
ex_ctrl_wb_memtoreg
ex_ctrl_wb_regwrite
mem_ctrl_wb_memtoreg
mem_ctrl_wb_regwrite
Signextend
Hazard
clk
2
hazard
dmem_wait
enable
ex_regdst_addr
0
id_instr_20_16
[15-11]
c31
Pipe_en
(This signal goes to all
registers on which no
write signal is depicted)
mem_alu_result
aluctrl
id_instr_10_6
[20-16]
[31-26]
[5-0]
0
ex_alu_result
id_instr_5_0
[10-6]
IFIDWrite
mux4
PCWrite
1
0
mux6
1
mux8
a
id_ctrl_ex_regdst
id_ctrl_ex_alusrc
id_ctrl_ex_aluop
id_ctrl_ex_target
id_ctrl_mem_branch
id_ctrl_ex_hilo_write
id_ctrl_ex_hiloalu_sel
id_ctrl_ex_regvalue
id_ctrl_mem_memwrite
id_ctrl_mem_memread
id_ctrl_wb_memtoreg
id_ctrl_wb_regwrite
mux3
w_addr_reg
ram_addr
signextend
byte
r_addr_reg2
memdev
r_data_reg1
registers
w_data_reg
if_instr
rom_r
[20-16]
branch_
ctrl
0
r_addr_reg1
decoder_nb
rom_wait
mux7
1
mux2
rom_dout
3
LCC compiler
4
LCC compiler
5
LCC compiler
Forwarding optie 1
if_pc
6
id_pc
1
add2
shiftleft
id_immediate
w
r_data_reg2
id_data_reg2
[15-0]
mux5
shiftleft_
jmp
ram_wait
ram_din
1
0
b
[25-0]
ram_addr
ram_r
ram_w
mem_dmem_data
hi
lo
2
2
decoder
0
1
[5-0]
IFIDWrite
1
id_instr_15_11
hazard_ctrl
ctrl
Enable
rst
mem_regdst_addr
ex_ctrl_wb_memtoreg
ex_ctrl_wb_regwrite
mem_ctrl_wb_memtoreg
mem_ctrl_wb_regwrite
Signextend
Hazard
clk
2
hazard
dmem_wait
enable
ex_regdst_addr
0
id_instr_20_16
[15-11]
c31
Pipe_en
(This signal goes to all
registers on which no
write signal is depicted)
mem_alu_result
aluctrl
id_instr_10_6
[20-16]
[31-26]
[5-0]
0
ex_alu_result
id_instr_5_0
[10-6]
mux4
PCWrite
1
0
mux6
1
mux8
a
id_ctrl_ex_regdst
id_ctrl_ex_alusrc
id_ctrl_ex_aluop
id_ctrl_ex_target
id_ctrl_mem_branch
id_ctrl_ex_hilo_write
id_ctrl_ex_hiloalu_sel
id_ctrl_ex_regvalue
id_ctrl_mem_memwrite
id_ctrl_mem_memread
id_ctrl_wb_memtoreg
id_ctrl_wb_regwrite
mux3
w_addr_reg
2
ram_dout
memdev
registers
w_data_reg
1
branch_
ctrl
r_addr_reg2
id_data_reg1
alu
r_data_reg1
mux2
[20-16]
if_instr
rom_r
decoder_nb
0
mux7
rom_wait
r_addr_reg1
mux
[25-21]
1
mux
rom_dout
dev_*
0
id_instr_25_0
rom_addr
signextend
byte
imm2word
0
mux1
pc
add1
c4
Forwarding optie 2
if_pc
7
id_pc
1
add2
shiftleft
imm2word
id_immediate
r_data_reg2
0
id_data_reg2
b
[25-0]
memdev
ram_r
ram_w
mem_dmem_data
hi
lo
2
2
decoder
0
1
[5-0]
IFIDWrite
1
id_instr_15_11
hazard_ctrl
ctrl
Enable
rst
mem_regdst_addr
ex_ctrl_wb_memtoreg
ex_ctrl_wb_regwrite
mem_ctrl_wb_memtoreg
mem_ctrl_wb_regwrite
Signextend
Hazard
clk
2
hazard
dmem_wait
enable
ex_regdst_addr
0
id_instr_20_16
[15-11]
c31
Pipe_en
(This signal goes to all
registers on which no
write signal is depicted)
mem_alu_result
aluctrl
id_instr_10_6
[20-16]
[31-26]
[5-0]
0
ex_alu_result
id_instr_5_0
[10-6]
mux4
PCWrite
1
0
mux6
1
mux8
a
id_ctrl_ex_regdst
id_ctrl_ex_alusrc
id_ctrl_ex_aluop
id_ctrl_ex_target
id_ctrl_mem_branch
id_ctrl_ex_hilo_write
id_ctrl_ex_hiloalu_sel
id_ctrl_ex_regvalue
id_ctrl_mem_memwrite
id_ctrl_mem_memread
id_ctrl_wb_memtoreg
id_ctrl_wb_regwrite
mux3
w
[15-0]
1
ram_addr
signextend
byte
w_addr_reg
ram_din
branch_
ctrl
registers
w_data_reg
ram_wait
alu
r_addr_reg2
2
ram_dout
id_data_reg1
mux2
r_data_reg1
mux
[20-16]
if_instr
rom_r
decoder_nb
0
mux7
rom_wait
r_addr_reg1
mux
[25-21]
1
1
mux5
id_instr_25_0
rom_addr
rom_dout
dev_*
0
shiftleft_
jmp
0
mux1
pc
add1
c4
Forwarding - aandachtspunten
8

Register 0 heeft altijd de waarde 0, ongeacht wat er in dit register wordt
geschreven
 Forward dus nooit register 0

Forward altijd de nieuwste data
 EX gaat voor MEM, MEM gaat voor WB, WB gaat voor ID

De twee register inputs kunnen uit dezelfde of verschillende pipeline stages
komen
 De twee forwarding multiplexers moeten los worden aangestuurd

De lees operaties (lw, lb) hebben 1 delay slot, de data uit het geheugen is
pas beschikbaar is in de WB stage
 Er kan een data hazard zijn tussen een load instructie in the MEM stage
en een instructie in de ID stage, deze kan niet worden opgelost met
forwarding
Forwarding – WB stage
9

Hazard detectie in WB stage
else if (memwbregwrite_t == 1 &&
((memwbwriteregister_t == ifidreadregister1_t) ||
(memwbwriteregister_t == ifidreadregister2_t)))
{
hazard = 1;
}

Forwading vanuit WB stage
if (memwbregwrite_t == 1 && memwbwriteregister_t == ifidreadregister1_t
&& memwbwriteregister_t != 0)
{
forwardA.write(3);
}
if (memwbregwrite_t == 1 && memwbwriteregister_t == ifidreadregister2_t
&& memwbwriteregister_t != 0)
{
forwardB.write(3);
}
if_pc
Lab 5 - Synthesis
id_pc
1
add2
shiftleft
imm2word
id_immediate
dev_*
id_instr_25_0
rom_addr
1
2
mux5
0
shiftleft_
jmp
0
mux1
add1
c4
pc
ram_dout
ram_wait
[25-21]
ram_din
id_data_reg1
1
w_addr_reg
w
r_data_reg2
0
id_data_reg2
b
alu
[15-0]
[25-0]
ram_addr
ram_r
ram_w
mem_dmem_data
hi
lo
2
2
decoder
dmem_wait
hazard_ctrl
ctrl
rst
mem_regdst_addr
ex_ctrl_wb_memtoreg
ex_ctrl_wb_regwrite
mem_ctrl_wb_memtoreg
mem_ctrl_wb_regwrite
Signextend
Enable
clk
2
mux4
1
id_instr_15_11
Hazard
enable
ex_regdst_addr
0
id_instr_20_16
[15-11]
c31
Pipe_en
(This signal goes to all
registers on which no
write signal is depicted)
mem_alu_result
aluctrl
id_instr_10_6
[20-16]
[31-26]
[5-0]
ex_alu_result
id_instr_5_0
[10-6]
IFIDWrite
0
0
1
[5-0]
PCWrite
1
mux8
1
0
mux6
a
id_ctrl_ex_regdst
id_ctrl_ex_alusrc
id_ctrl_ex_aluop
id_ctrl_ex_target
id_ctrl_mem_branch
id_ctrl_ex_hilo_write
id_ctrl_ex_hiloalu_sel
id_ctrl_ex_regvalue
id_ctrl_mem_memwrite
id_ctrl_mem_memread
id_ctrl_wb_memtoreg
id_ctrl_wb_regwrite
signextend
byte
if_instr
registers
w_data_reg
mux3
r_data_reg1
r_addr_reg2
memdev
r_addr_reg1
[20-16]
branch_
ctrl
0
rom_r
decoder_nb
rom_wait
mux7
1
mux2
rom_dout
hazard
10
11
Design flow
test
LCC C
Compiler
implementation
Application
(C sources)
LCC C
Compiler
Celoxica
create memory
sw
hardware
simulator
Celoxica
transfer
hw
Visual
C++
mMIPS
(C++ sources
that use
SystemC
library)
CoCentric
SystemC
Compiler
Xilinx XST
Xilinx ISE
12
Design flow
www.es.ele.tue.nl/education/5JJ55-65/mmips-lab/labs/5/toolflow.php