1CSNW1 - voti.nl

1CSNW1
Computersystemen en
Netwerken
Adrie van Doesburg
Leo van Moergestel
Jan Nijman
 Wouter van Ooijen
Cursusinformatie
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Site:
https://www.sharepoint.hu.nl/cursussen/fnt/TCTF-V1CSNW1-04
http://wwwvoti.nl/hvu/V1CSNW1
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Boek:
Computersystemen en embedded systemen
L.J.M. van Moergestel
Academic Service
ISBN 978-90-395-2528-9
CSNW1 lesprogramma
Week 1: Processors, bussystemen
Week 2: Dataopslag
Week 3: Datacommunicatie
Week 4: Computernetwerken, ISO/OSI model
Week 5: Ethernet
Week 6: Internet
Week 7: Inleiding Operating Systems
proeftentamen
Computersysteem (herh.)
PU(s)
MEMORY
I/O
Adresbus
databus
besturingsbus
Von Neumann cyclus (herh.)
Exception
Cycle
EX
IF
ID
Von Neumann machine (herh.)
1001101101100011
Instruction register
1001001001001110
controle
Registers
memory
and I/O
unit
1001001001001110
0011100101111010
PC
Stack pointer
Status register
ALU
Konrad Zuse's First Computer
The Z1 (1936, relais)
Bron: www.epemag.com/zuse
Integrated circuit
Jack Kilby (JK-Flip/Flop) 1959, TI
The Chip that Jack Built Changed the World
Bron: www.ti.com/corp/docs/kilbyctr/jackbuilt.shtml
Microprocessor
(Intel 1971)
Ted Hoff
• Intel: 4004 Processor
• 2300 Transistoren
• 10 um technologie
• 0,108 MHz
Bron: /www.intel.com/museum/archives/4004.htm
Core 2 Duo (Intel 2006)
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Core 2 Duo
291M transistoren
65 nm technologie
1-3,3 GHz
Bron: www.intel.com
RISC versus CISC
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Complex instruction set computer (CISC):
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many addressing modes;
complex operations.
Reduced instruction set computer (RISC):
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load/store;
simple operations
pipelinable instructions.
RISC
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De instructies verrichten simpele taken
Alle instructies zijn even groot
Er is geen uitgebreide keuze aan adresseermodes
Er zijn veel interne registers beschikbaar
Load and Store architecture
Pipelining
Superscalaire
instructieafhandeling
Super Pipelining
Super Pipelining (2)
Kenmerken Processoren
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Architectuur
Programmeermodel
Instructieset
Technologie (fabricage)
ARM Processor Architecture
Core 2 Duo Architecture
Bron: www.zdnet.com.au
Cell Processor Architecture
(Sony Playstation 3)
Bron: H.P. Hofstee
Programmeermodellen
Instructieset (herh.)
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Verplaatsing
Bewerking
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(and, or, lsl, … )
(add, sub, mul, … )
Sprong
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Logisch
Rekenkundig
(mov, ldr, str)
Conditioneel
(beq, bne, … )
Niet conditioneel (jmp, bra, … )
Subroutine aanroep (call, ret, …)
Speciale instructies (nop, hlt, swi, … )
Bus hierarchie
Timing: Asynchrone Bus
Timing: Synchrone Bus
PCI gebaseerd computersysteem
PCI-bus Burst Transfer
Accellerated Graphics Port (AGP)
Intel PM855 Chipset
Bron: www.intel.com
PCI Express Based System
Bron: AV Bhatt, Intel
PCI
Express
Lanes
Bron: AV Bhatt, Intel
PCI Express Layers
Bron: AV Bhatt, Intel
USB Architectuur
USB Hubs
Universal Serial Bus (USB)
• A Low Speed rate of 1.5 Mbits/sec that is mostly used for Human
Interface Devices (HID) such as keyboards, mice and joysticks.
• A Full Speed rate of 12 Mbit/s.
• A Hi-Speed rate of 480 Mbit/s.
• Plug and play
• Hot swap
• Power supply 5 V, 500 mA
USB signals are transmitted on a twisted pair of data cables, labelled D+
and D−.
These collectively use half-duplex differential signalling.
Transmitted signal levels are 0.0–0.3 V for low and 2.8–3.6 V for high.
Practicum - ZEP2 Simulator
Links
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CPU (Wikipedia)
Intel Processors Site
SIMD (Wikipedia)
DSP (Wikipedia)
Computer Bus (Wikipedia)
PCI-bus (Wikipedia)
PCI Express (Wikipedia)
USB in a Nutshell
Firewire (Wikipedia)
Opdrachten
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Bestudeer 8.1 t/m 8.3 en 8.6
Lees PCI-express whitepaper
Maak opgaven 8.1 t/m 8.5